yosys

Run synthesis on Verilog file

$ yosys -p "synth -top [module]" [design.v]

$ yosys

$ yosys -s [script.ys]

$ yosys -p "synth -top [module]" -o [output.json] [design.v]

$ yosys -S [design.v]

$ yosys -c [script.tcl]

$ yosys -H

$ yosys -h [synth]

yosys [options] [infile...]

yosys is an open source framework for RTL synthesis. It reads Verilog hardware description language and synthesizes it to gate-level netlists for various target technologies.
The tool provides an interactive shell with numerous commands for reading designs, elaboration, optimization, technology mapping, and writing outputs. Synthesis flows are defined through script files or command-line arguments.
Supported input formats include Verilog, RTLIL, and Liberty. Output formats include BLIF, EDIF, JSON, Verilog, and various FPGA-specific formats. The tool supports plugins for extending functionality.
Yosys is widely used in open-source FPGA toolchains including Lattice iCE40 and ECP5 flows with nextpnr.

-s scriptfile

Execute commands from script file.

Execute TCL script file.

Execute command(s).

Write design to file on exit.

Frontend for input files.

Backend for output file.

Load plugin module.

Write log to file.

Quiet operation (errors only).

Log verbosity level.

Add timestamps to log.

Shortcut for synth command.

Print command list.

Help for specific command.

Suppress banner.

Suppress footer.

SystemVerilog support is limited. Complex designs may require multiple synthesis passes. Some features need external plugin modules. Memory and timing optimization may need manual tuning.

yosys was created by Clifford Wolf (now Claire Wolf) and released in 2012. It became the foundation of open-source FPGA toolchains, enabling fully open synthesis flows. The project is now maintained by YosysHQ and remains central to the open FPGA ecosystem.

nextpnr(1), iverilog(1), verilator(1)