iverilog

Compile a source file into an executable

$ iverilog [path/to/source.v] -o [path/to/executable]

$ iverilog [path/to/source.v] -Wall -o [path/to/executable]

$ iverilog -o [path/to/executable] -tvvp [path/to/source.v]

$ iverilog [path/to/source.v] -o [path/to/executable] -I[path/to/library_directory]

$ iverilog -E [path/to/source.v]

iverilog [options] <filename> [filename...]

-o <output_filename>
    Specifies the output filename for the compiled executable. The default is a.out.

-c <command_file>
    Reads Verilog options from the specified command file, allowing complex configurations.

-D <macro>[=<value>]
    Defines a macro with an optional value, similar to the C preprocessor's #define directive.

-I <directory>
    Adds a directory to the list of paths searched for `include files, controlling where the compiler looks for included source code.

-M <macro_file>
    Writes a list of defined macros to a file, which can be useful for generating make dependencies.

-P <param>=<value>
    Sets a top-level module parameter value, allowing configuration of generic designs.

-s <top_module>
    Specifies the top-level module to elaborate. This is crucial for designs with multiple potential top modules.

-t <target>
    Specifies the compilation target. Common targets include vvp (default, for simulation), null (for syntax checking only), and fpga (for specific FPGA flows).

-v
    Enables verbose messages during compilation, providing more detailed output about the process.

-V
    Prints version information for iverilog and then exits.

-g<option>
    Enables specific language extensions or optimizations (e.g., -g2005 for Verilog-2005 features, -gstrict-ca for strict combinational always blocks).

-y <library_dir>
    Adds a directory to the list of paths searched for Verilog library modules, aiding in resolving module instantiations.

-f <filelist>
    Reads source filenames from a specified filelist, with one filename per line, simplifying large project compilation.

-Wall, -Werror
    -Wall enables all warnings. -Werror treats all warnings as compilation errors, enforcing stricter code quality.

iverilog is the open-source Icarus Verilog compiler, a powerful tool for compiling Verilog Hardware Description Language (HDL) code. It translates Verilog source files into an executable format, typically a bytecode file (often with .vvp extension), which can then be simulated using the vvp (Icarus Verilog simulator) command.

iverilog supports a wide range of Verilog standards, including IEEE 1364-2005 (Verilog-2005) and significant portions of SystemVerilog (IEEE 1800-2009/2012). It is widely used for design verification, behavioral simulation, and synthesis preparation in digital circuit design. Its capabilities include pre-processing, parsing, elaboration, and code generation, making it a complete solution for Verilog compilation.

iverilog plays a crucial role in the open-source EDA toolchain, providing a free alternative to commercial Verilog compilers and simulators, enabling hobbyists, students, and professionals to design and test digital circuits efficiently.

While iverilog supports a significant portion of SystemVerilog, it does not have full SystemVerilog support, especially for advanced verification constructs like classes, interfaces, and assertions. Its primary focus remains on design and behavioral aspects.

SDF annotation support might be limited compared to commercial tools. Performance for very large designs can be a consideration, although it is generally very efficient for its scope and capabilities.

iverilog typically compiles Verilog source files into an intermediate bytecode file (e.g., a.out by default, or as specified with -o). This bytecode is then executed by the vvp simulator to perform the simulation. For instance:
iverilog -o my_design.vvp my_design.v testbench.v
vvp my_design.vvp

iverilog attempts to automatically identify the top-level module if only one uninstantiated module exists in the source files. However, if a design contains multiple potential top-level modules or you need to explicitly specify the root of the design hierarchy, the -s option is essential to direct the compiler accordingly.

Icarus Verilog was initiated by Stephen Williams in 1998 with the ambitious goal of creating a complete, open-source Verilog compiler and simulator. Since its inception, it has undergone continuous development and improvement, progressively evolving to support newer Verilog standards such as Verilog-2001, Verilog-2005, and significant portions of SystemVerilog.

It has become a cornerstone of the open-source Electronic Design Automation (EDA) community, providing a free and accessible entry point for digital hardware design and verification. Its stable development, robust feature set, and strong community support have made it a widely adopted tool for both educational institutions and professional applications.

vvp(1): The Icarus Verilog runtime simulator, which executes the bytecode output generated by iverilog., gtkwave(1): A widely used open-source waveform viewer for VCD/FST files, commonly used to visualize simulation results from iverilog/vvp., verilator(1): Another open-source Verilog compiler that translates Verilog to C++/SystemC for faster simulation of designs., yosys(1): An open-source HDL synthesis framework, often used in conjunction with iverilog for synthesis preparation and analysis.