iverilog

Compile a source file into an executable

$ iverilog [path/to/source.v] -o [path/to/executable]

$ iverilog [path/to/source.v] -Wall -o [path/to/executable]

$ iverilog -o [path/to/executable] -tvvp [path/to/source.v]

$ iverilog [path/to/source.v] -o [path/to/executable] -I[path/to/library_directory]

$ iverilog -E [path/to/source.v]

iverilog [-options] file.v [file2.v ...] [-o output.vvp]

-o file
    Specify output file name (default: a.out)

-t target
    Select target format (default: vvp; others: null, vvp_api, foreign)

-p param=value
    Override Verilog parameter or define macro

-I dir
    Add directory to search path for `include files

-y dir
    Add library directory for -v/-m modules

-Wall
    Enable all warning messages

-Winfloop
    Warn about infinite loops in combinational logic

-v
    Verbose output, list modules/dependencies

-g
    Select language subset (e.g., -g2001, -g2005, -gsv2009)

-N
    Nexus gate library target

-s
    Strict compliance mode

-l lib
    Link with VVP support library

-m mm
    Load module mm from library

Icarus Verilog (iverilog) is an open-source compiler that translates Verilog HDL source code into an intermediate format, primarily for simulation purposes. It supports most IEEE Std 1364-1995, 1364-2001, 1364-2005, and portions of SystemVerilog (IEEE 1800). The tool compiles Verilog designs into VVP (Vera Virtual Processor) assembly code, which is then executed by the vvp runtime simulator.

Key features include support for synthesizable Verilog subsets, behavioral modeling, gate-level netlists, and PLI/VPI interfaces for advanced verification. It's widely used in FPGA/ASIC design flows for quick simulation and regression testing, especially in academic and hobbyist environments due to its lightweight nature and no-cost license.

Usage involves specifying input Verilog files, options for optimization, parameter overrides, and output files. It excels in parsing large designs and offers good performance for RTL simulation but may lack some commercial tool optimizations for timing analysis or full SystemVerilog assertions.

Limited SystemVerilog support; not fully synthesizable for all constructs. Requires vvp for execution. Parsing errors common with non-standard code.

Compile: iverilog -o design.vvp design.v
Simulate: vvp design.vvp

Default vvp for simulation; -tforeign for C++ DLL export.

Developed by Stephen Williams starting in 1998 as free Verilog simulator. Actively maintained; version 12.x supports enhanced SystemVerilog features. Popular in open-source FPGA communities.

vvp(1), gtkwave(1), verilator(1)