iverilog
icarus Verilog compiler
TLDR
Compile Verilog file
$ iverilog -o [output] [input.v]
Compile multiple files$ iverilog -o [output] [file1.v] [file2.v]
Specify top module$ iverilog -s [top_module] -o [output] [input.v]
Generate VCD output$ iverilog -o [output] [input.v] && vvp [output]
Include directory$ iverilog -I [include_dir] -o [output] [input.v]
Define macro$ iverilog -D[MACRO=value] -o [output] [input.v]
SYNOPSIS
iverilog [options] file...
DESCRIPTION
iverilog is the Icarus Verilog compiler. It compiles Verilog HDL to simulation executables.
The tool supports IEEE Verilog standards. Output runs with vvp simulator for verification and testing.
PARAMETERS
-o FILE
Output file name.-s MODULE
Specify top-level module.-I DIR
Add include directory.-D MACRO
Define preprocessor macro.-g STANDARD
Verilog standard (2001, 2005, 2009, 2012).-t TARGET
Target format (vvp, null).--help
Display help information.
CAVEATS
Simulation only, not synthesis. Some SystemVerilog limited. Output requires vvp runtime.
HISTORY
Icarus Verilog was created by Stephen Williams as an open-source alternative to commercial Verilog simulators.