iverilog

Simulate Verilog hardware designs

TLDR

Compile a source file into an executable

$ iverilog [path/to/source.v] -o [path/to/executable]

Compile a source file into an executable while displaying all warnings

$ iverilog [path/to/source.v] -Wall -o [path/to/executable]

Compile and run explicitly using the VVP runtime

$ iverilog -o [path/to/executable] -tvvp [path/to/source.v]

Compile using Verilog library files from a different path

$ iverilog [path/to/source.v] -o [path/to/executable] -I[path/to/library_directory]

Preprocess Verilog code without compiling

$ iverilog -E [path/to/source.v]

-g{1995,2001,2001-noconfig,2005,2005-noconfig,2009,2012}
    Specify the Verilog language standard version to use.

-o
    Specify the name of the output file.

-s
    Specify the top-level module to simulate.

-I
    Add a directory to the include search path.

-D =
    Define a preprocessor macro.

-y
    Add a directory to the library search path.

-v
    Specify a library file.

-m
    Specify a module that should be treated as a system task.

-M
    Use module as a library

-T
    Enable tracing information.

-W
    Report specific warning based on keyword.

-E
    Preprocess only. Does not compile the result.

-h
    Display help message.

-B
    Specify a path to search for executables and runtime support files.

DESCRIPTION

Icarus Verilog is a free software Verilog simulation and synthesis tool. It compiles Verilog design into some target format. Currently, it supports compiling to a virtual machine for simulation, to C++ for evaluation, and to synthesis. The simulator can execute a simulation of the compiled design, and provides debugging and waveform viewing capabilities. It is useful for verifying hardware designs, simulating behavior before implementation, and can be integrated into larger hardware development workflows. Icarus Verilog supports a large subset of the IEEE 1364-2005 Verilog HDL standard. It's command-line driven, enabling automation through scripts and integration with other EDA (Electronic Design Automation) tools.

CAVEATS

Icarus Verilog does not fully support all aspects of the Verilog standard, especially SystemVerilog. Synthesis capabilities are still under development and might not produce optimal results.

SIMULATION

The compiled output of iverilog is often executed by vvp (Icarus Verilog Virtual Machine). This allows for simulation of the hardware described in the Verilog source code. Waveform viewers like GTKWave can be used to visualize the simulation results.

SYNTHESIS

While simulation is the primary focus, iverilog includes basic synthesis capabilities, allowing you to convert Verilog code into a gate-level netlist that can potentially be used for implementation on FPGAs or ASICs. However, for complex designs, more advanced synthesis tools are generally preferred.

HISTORY

Icarus Verilog was initially developed by Steve Williams. It has been continuously improved by a community of developers and has become a popular open-source choice for Verilog simulation and synthesis. It has been used in various academic and industrial projects.