verilator

Lint Verilog

$ verilator --lint-only [design.v]

$ verilator --cc [design.v]

$ verilator --cc [design.v] --exe [testbench.cpp]

$ verilator --cc [design.v] --exe [tb.cpp] --build

$ verilator --cc [design.v] --trace

verilator [--lint-only] [--cc] [--trace] [options] files

verilator converts synthesizable Verilog and SystemVerilog designs into optimized C++ or SystemC models. The generated code compiles to native executables that run significantly faster than interpreted simulators, making it one of the fastest open-source Verilog simulators available.
The tool also functions as a lint checker with --lint-only, catching common coding errors and style issues without generating simulation code. Waveform tracing can be enabled with --trace to produce VCD files for viewing in waveform viewers like GTKWave.

--lint-only

Lint check only.

Generate C++.

Create executable.

Compile output.

Enable waveforms.

All warnings.

Not full simulator. Cycle-based. Synthesizable subset.

Verilator was created by Wilson Snyder as the fastest Verilog simulator through C++ compilation.

iverilog(1), gtkwave(1), yosys(1)