make

Call the first target specified in the Makefile (usually named "all")

$ make

$ make [target]

$ make [[-j|--jobs]] [4] [target]

$ make [[-f|--file]] [path/to/file]

$ make [[-C|--directory]] [path/to/directory]

$ make [[-B|--always-make]] [target]

$ make [target] [variable]=[new_value]

$ make [[-e|--environment-overrides]] [target]

make [options] [target ...]

-f makefile
    Specifies the makefile to use. If not specified, make searches for files named makefile or Makefile.

-i, --ignore-errors
    Ignores all errors encountered during the execution of commands.

-k, --keep-going
    Continues building other targets even if some targets fail.

-n, --just-print, --dry-run, --recon
    Prints the commands that would be executed, but does not actually execute them.

-p, --print-data-base
    Prints make's internal rule set and variable definitions.

-r, --no-builtin-rules
    Disables the built-in implicit rules.

-s, --silent, --quiet
    Suppresses the printing of commands before executing them.

-v, --version
    Prints the make version number.

-C dir
    Changes to directory dir before reading the makefiles or doing anything else.

-j [jobs], --jobs[=jobs]
    Specifies the number of jobs (commands) to run simultaneously. If jobs is omitted, make runs as many jobs as possible.

The make command is a powerful utility that automates the building of executable programs and libraries from source code. It reads a file called a makefile, which specifies dependencies between files (typically source code files) and commands to be executed to create target files. make intelligently rebuilds only the parts of the project that have changed since the last build, saving significant time during development.
It determines which pieces of code need to be recompiled and automatically issues the commands to recompile them. make is a foundational tool in software development, especially for projects with multiple source files and complex dependencies, ensuring a consistent and repeatable build process.
The core function of make is to execute a sequence of commands to transform a set of source files into an executable program or library. The commands and dependencies are defined in a makefile. make reads this makefile and determines the order in which the commands must be executed, based on the dependencies between the files.

Makefiles can be complex and require a good understanding of dependencies and shell scripting. Debugging makefiles can be challenging.
make relies heavily on timestamps to determine if a file needs to be rebuilt. Incorrect system time can lead to unexpected behavior.

A makefile consists of a set of rules, each of which specifies how to build a target file from its dependencies. A rule typically includes a target, a list of dependencies, and a set of commands to execute. Example: target: dependency1 dependency2 command1 command2

Makefiles support variables to store values that can be used throughout the makefile. Variables can be defined using the = operator. They are referenced using $(variable_name).

The make utility was originally created by Stuart Feldman at Bell Labs in 1976. It was designed to automate the compilation process and manage dependencies in software projects. Its initial purpose was to reduce the manual effort required to rebuild software after changes were made. Over time, make has evolved and been widely adopted as a standard tool in software development, with various implementations and extensions.

gcc(1), ar(1), ld(1)