spike

RISC-V reference ISA simulator

TLDR

Run simulator

$ spike [program.elf]

With ISA extension specification

$ spike --isa=rv64gc [program.elf]

Interactive debug

$ spike -d [program.elf]

Simulate with 4 cores

$ spike -p4 [program.elf]

With memory configuration (base:size)

$ spike -m0x80000000:0x10000000 [program.elf]

Log executed instructions

$ spike -l --isa=rv64gc [program.elf]

SYNOPSIS

spike [--isa spec] [-d] [-p n] [options] program

spike is the official RISC-V ISA (Instruction Set Architecture) reference simulator. It provides instruction-accurate emulation of RISC-V processors, supporting both RV32 and RV64 base integer instruction sets along with standard extensions including M (multiply/divide), A (atomic), F/D (floating-point), and C (compressed).
The simulator includes an interactive debug mode for stepping through instructions, setting breakpoints, and inspecting registers and memory. It supports multi-core SMP simulation with configurable processor counts and memory layouts, making it suitable for testing both bare-metal firmware and operating system kernels.
As the reference implementation maintained by the RISC-V project, spike serves as the golden model for verifying hardware implementations and compiler output against the specification.

PARAMETERS

--isa SPEC

ISA specification.

-d

Debug mode.

-p N

Number of processors.

-m RANGE

Memory configuration.

--pc ADDR

Start address.

-l

Log executed instructions

-g

Track histogram of PCs

-h

Print help message

--ic= S:W:B

Instantiate instruction cache (sets:ways:blocksize)

--dc= S:W:B

Instantiate data cache (sets:ways:blocksize)

--l2= S:W:B

Instantiate L2 cache (sets:ways:blocksize)

CAVEATS

Instruction-level simulation only; no cycle accuracy. Intended as a development and verification tool, not for performance estimation.

HISTORY

spike is the official RISC-V ISA simulator, developed as the reference implementation for the RISC-V architecture.