ghdl

Analyze a VHDL source file and produce an object file

$ ghdl -a [filename.vhdl]

$ ghdl -e [design]

$ ghdl -r [design]

$ ghdl -r [design] --wave=[output.ghw]

$ ghdl -s [filename.vhdl]

$ ghdl --help

ghdl MODE [options] FILE...
Common usage modes:
ghdl -a [options] VHDL_FILE...
ghdl -e [options] TOP_LEVEL_ENTITY
ghdl -r [options] TOP_LEVEL_ENTITY
ghdl --clean

-a, --analyze
    Analyzes VHDL source files and compiles them into a working library. This is the crucial first step for any VHDL design in GHDL.

-e, --elaborate
    Elaborates a top-level entity or configuration. This step links all analyzed design units and prepares the design for simulation by resolving generics and port maps.

-r, --run
    Runs the elaborated design. This executes the simulation, producing any specified outputs or waveforms and reporting simulation results.

--synth
    Performs synthesis analysis. GHDL checks the VHDL code for synthesizable constructs, which is vital for designs intended for FPGA or ASIC implementation.

-m, --make
    Combines analysis and elaboration steps. It automatically analyzes dependencies and elaborates the specified top-level unit, simplifying the workflow.

--clean
    Removes all generated GHDL files (e.g., compiled units, executables, waveforms) from the current working directory or specified library.

-P, --workdir=DIR
    Specifies the working directory for libraries. This option allows users to organize compiled VHDL units in a structured manner for complex projects.

--std=VHDL_STANDARD
    Selects the VHDL standard to use for compilation (e.g., 87, 93, 02, 08). Ensures compatibility with different VHDL language versions.

--wave=FORMAT
    Enables waveform dumping during simulation. Common formats are fst or vcd for viewing with external tools like GTKWave, aiding in debugging.

GHDL (GNAT Hybrid Design Language) is a free and open-source VHDL simulator that compiles VHDL source files directly into native machine code. This approach significantly enhances simulation performance compared to interpreted simulators. GHDL supports various VHDL standards, including VHDL-87, VHDL-93, V2002, and VHDL-2008. It serves as a crucial tool in the electronic design automation (EDA) ecosystem, allowing engineers to analyze, elaborate, and simulate digital circuits described in VHDL, making it suitable for both functional verification and synthesis analysis. Its integration capabilities make it a popular choice for continuous integration (CI) workflows in hardware development.

While GHDL provides excellent VHDL language support, it may not fully support all vendor-specific VHDL extensions or advanced features found in commercial simulators. Its primary focus is on VHDL simulation and not on integrated debugging features, which typically rely on external waveform viewers.
Performance can vary significantly depending on the complexity of the VHDL design and the underlying system resources.

A common GHDL workflow involves three distinct steps: analysis (-a), elaboration (-e), and simulation (-r). First, individual VHDL files are analyzed and compiled into a working library. Next, a top-level entity or configuration is elaborated, linking all the analyzed units and creating an executable. Finally, the elaborated design is simulated to verify its functionality. The --make option can often simplify this by combining analysis and elaboration into a single command.

For debugging and visualizing signal activity during simulation, GHDL can generate waveform dump files. Using the --wave option with a format like fst or vcd creates a file that can be opened and inspected by external waveform viewers such as GTKWave. This allows users to observe the timing and values of internal signals and primary outputs throughout the simulation, which is crucial for verifying design correctness.

GHDL was initially developed by Tristan Gingold as an open-source project to provide a free, high-performance VHDL simulator. It distinguished itself by compiling VHDL code to native machine code using the GCC backend, a technique that has significantly contributed to its speed and efficiency. Over the years, GHDL's development has been continuous, expanding its VHDL standard support, improving compatibility, and becoming a staple for open-source digital hardware development and verification.

gtkwave(1), iverilog(1), yosys(1)