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ghdl

Open-source VHDL simulator and synthesizer

TLDR

Analyze VHDL file
$ ghdl -a [file.vhdl]
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Elaborate design
$ ghdl -e [entity_name]
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Run simulation
$ ghdl -r [entity_name]
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Run with VCD waveform output
$ ghdl -r [entity_name] --vcd=[output.vcd]
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Run with GHW waveform output
$ ghdl -r [entity_name] --wave=[output.ghw]
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Run simulation with stop time
$ ghdl -r [entity_name] --stop-time=[100ns]
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Import files
$ ghdl -i [file.vhdl]
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Syntax check only
$ ghdl -s [file.vhdl]
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SYNOPSIS

ghdl command [options] files

DESCRIPTION

ghdl is an open-source VHDL simulator and synthesizer. It analyzes, elaborates, and simulates VHDL designs, supporting VHDL-87, VHDL-93, VHDL-2002, and VHDL-2008 standards.
The typical workflow involves three steps: analyzing source files (-a) to check syntax and compile, elaborating the design hierarchy (-e) to resolve all dependencies, and running the simulation (-r). Waveform outputs in VCD and GHW formats can be generated for viewing in tools like GTKWave.

PARAMETERS

-a FILE

Analyze VHDL source file.
-e ENTITY
Elaborate design entity.
-r ENTITY
Run simulation.
-i FILE
Import VHDL file.
-s FILE
Syntax check only.
--vcd FILE
Generate VCD waveform output.
--wave FILE
Generate GHW waveform output.
--stop-time TIME
Simulation stop time (e.g., 100ns, 1us, 10ms).
--std STANDARD
VHDL standard to use: 87, 93, 93c, 00, 02, 08.
--work NAME
Set the work library name.
--ieee LIBRARY
Select IEEE library flavor: standard, synopsys, mentor.
--help
Display help information.

CAVEATS

Some advanced VHDL features may have limitations. Synthesis support is experimental. Large simulations can be memory-intensive.

HISTORY

GHDL was started by Tristan Gingold and is written in Ada. It provides a free software alternative to commercial VHDL simulators.

SEE ALSO

> TERMINAL_GEAR

Curated for the Linux community

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