iverilog
Preprocesses and compiles Verilog HDL (IEEE-1364) code, into executable programs for simulation.
TLDR
Compile a source file into an executable
>_ iverilog [source.v] -o [executable]
Also display all warnings
>_ iverilog [source.v] -Wall -o [executable]
Compile and run explicitly using the VVP runtime
>_ iverilog -o [execuable] -tvvp [source.v]
Compile using Verilog library files from a different path
>_ iverilog [source.v] -o [executable] -I[path/to/library_directory]
Preprocess Verilog code without compiling
>_ iverilog -E [source.v]
