iverilog

Preprocesses and compiles Verilog HDL (IEEE-1364) code, into executable programs for simulation.

TLDR

Compile a source file into an executable

>_ iverilog [source.v] -o [executable]
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Also display all warnings

>_ iverilog [source.v] -Wall -o [executable]
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Compile and run explicitly using the VVP runtime

>_ iverilog -o [execuable] -tvvp [source.v]
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Compile using Verilog library files from a different path

>_ iverilog [source.v] -o [executable] -I[path/to/library_directory]
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Preprocess Verilog code without compiling

>_ iverilog -E [source.v]
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