- Assemble a file, writing the output to a.out:as [file.s]- Assemble the output to a given file:as [file.s] -o [out.o]- Generate output faster by skipping whitespace and comment preprocessing. (Should only be used for trusted compilers):as -f [file.s]- Include a given path to the list of directories to search for files specified in .include directives:as -I [path/to/directory] [file.s]
as [-a[cdghlns][=file]] [--alternate] [-D] [--compress-debug-sections] [--nocompress-debug-sections] [--debug-prefix-map old=new] [--defsym sym=val] [-f] [-g] [--gstabs] [--gstabs+] [--gdwarf-2] [--gdwarf-sections] [--help] [-I dir] [-J] [-K] [-L] [--listing-lhs-width=NUM] [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM] [--listing-cont-lines=NUM] [--keep-locals] [--no-pad-sections] [-o objfile] [-R] [--hash-size=NUM] [--reduce-memory-overheads] [--statistics] [-v] [-version] [--version] [-W] [--warn] [--fatal-warnings] [-w] [-x] [-Z] [@FILE] [--sectname-subst] [--size-check=[error|warning]] [--elf-stt-common=[no|yes]] [--target-help] [target-options] [--|files ...]
Target AArch64 options: [-EB|-EL] [-mabi=ABI]
Target Alpha options: [-mcpu] [-mdebug | -no-mdebug] [-replace | -noreplace] [-relax] [-g] [-Gsize] [-F] [-32addr]
Target ARC options: [-mcpu=cpu] [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS] [-mcode-density] [-mrelax] [-EB|-EL]
Target ARM options: [-mcpu=processor[+extension...]] [-march=architecture[+extension...]] [-mfpu=floating-point-format] [-mfloat-abi=abi] [-meabi=ver] [-mthumb] [-EB|-EL] [-mapcs-32|-mapcs-26|-mapcs-float| -mapcs-reentrant] [-mthumb-interwork] [-k]
Target Blackfin options: [-mcpu=processor[-sirevision]] [-mfdpic] [-mno-fdpic] [-mnopic]
Target CRIS options: [--underscore | --no-underscore] [--pic] [-N] [--emulation=criself | --emulation=crisaout] [--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]
Target D10V options: [-O]
Target D30V options: [-O|-n|-N]
Target EPIPHANY options: [-mepiphany|-mepiphany16]
Target H8/300 options: [-h-tick-hex]
Target i386 options: [--32|--x32|--64] [-n] [-march=CPU[+EXTENSION...]] [-mtune=CPU]
Target i960 options: [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB| -AKC|-AMC] [-b] [-no-relax]
Target IA-64 options: [-mconstant-gp|-mauto-pic] [-milp32|-milp64|-mlp64|-mp64] [-mle|mbe] [-mtune=itanium1|-mtune=itanium2] [-munwind-check=warning|-munwind-check=error] [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] [-x|-xexplicit] [-xauto] [-xdebug]
Target IP2K options: [-mip2022|-mip2022ext]
Target M32C options: [-m32c|-m16c] [-relax] [-h-tick-hex]
Target M32R options: [--m32rx|--[no-]warn-explicit-parallel-conflicts| --W[n]p]
Target M680X0 options: [-l] [-m68000|-m68010|-m68020|...]
Target M68HC11 options: [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg] [-mshort|-mlong] [-mshort-double|-mlong-double] [--force-long-branches] [--short-branches] [--strict-direct-mode] [--print-insn-syntax] [--print-opcodes] [--generate-example]
Target MCORE options: [-jsri2bsr] [-sifilter] [-relax] [-mcpu=[210|340]]
Target Meta options: [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
Target MIPS options: [-nocpp] [-EL] [-EB] [-O[optimization level]] [-g[debug level]] [-G num] [-KPIC] [-call_shared] [-non_shared] [-xgot [-mvxworks-pic] [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] [-mfp64] [-mgp64] [-mfpxx] [-modd-spreg] [-mno-odd-spreg] [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2] [-mips64r3] [-mips64r5] [-mips64r6] [-construct-floats] [-no-construct-floats] [-mignore-branch-isa] [-mno-ignore-branch-isa] [-mnan=encoding] [-trap] [-no-break] [-break] [-no-trap] [-mips16] [-no-mips16] [-mmicromips] [-mno-micromips] [-msmartmips] [-mno-smartmips] [-mips3d] [-no-mips3d] [-mdmx] [-no-mdmx] [-mdsp] [-mno-dsp] [-mdspr2] [-mno-dspr2] [-mdspr3] [-mno-dspr3] [-mmsa] [-mno-msa] [-mxpa] [-mno-xpa] [-mmt] [-mno-mt] [-mmcu] [-mno-mcu] [-minsn32] [-mno-insn32] [-mfix7000] [-mno-fix7000] [-mfix-rm7000] [-mno-fix-rm7000] [-mfix-vr4120] [-mno-fix-vr4120] [-mfix-vr4130] [-mno-fix-vr4130] [-mdebug] [-no-mdebug] [-mpdr] [-mno-pdr]
Target MMIX options: [--fixed-special-register-names] [--globalize-symbols] [--gnu-syntax] [--relax] [--no-predefined-symbols] [--no-expand] [--no-merge-gregs] [-x] [--linker-allocated-gregs]
Target Nios II options: [-relax-all] [-relax-section] [-no-relax] [-EB] [-EL]
Target NDS32 options: [-EL] [-EB] [-O] [-Os] [-mcpu=cpu] [-misa=isa] [-mabi=abi] [-mall-ext] [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext] [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div] [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext] [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs] [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax] [-mb2bb]
Target PDP11 options: [-mpic|-mno-pic] [-mall] [-mno-extensions] [-mextension|-mno-extension] [-mcpu] [-mmachine]
Target picoJava options: [-mb|-me]
Target PowerPC options: [-a32|-a64] [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64| -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge| -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6| -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2| -mcell|-mspe|-mtitan|-me300|-mcom] [-many] [-maltivec|-mvsx|-mhtm|-mvle] [-mregnames|-mno-regnames] [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] [-msolaris|-mno-solaris] [-nops=count]
Target RL78 options: [-mg10] [-m32bit-doubles|-m64bit-doubles]
Target RX options: [-mlittle-endian|-mbig-endian] [-m32bit-doubles|-m64bit-doubles] [-muse-conventional-section-names] [-msmall-data-limit] [-mpid] [-mrelax] [-mint-register=number] [-mgcc-abi|-mrx-abi]
Target RISC-V options: [-march=ISA] [-mabi=ABI]
Target s390 options: [-m31|-m64] [-mesa|-mzarch] [-march=CPU] [-mregnames|-mno-regnames] [-mwarn-areg-zero]
Target SCORE options: [-EB][-EL][-FIXDD][-NWARN] [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] [-march=score7][-march=score3] [-USE_R1][-KPIC][-O0][-G num][-V]
Target SPARC options: [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3 -Asparcvisr|-Asparc5] [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5 -bump] [-32|-64] [--enforce-aligned-data][--dcti-couples-detect]
Target TIC54X options: [-mcpu=54|-mcpu=54lp] [-mfar-mode|-mf] [-merrors-to-file <filename>|-me <filename>]
Target TIC6X options: [-march=arch] [-mbig-endian|-mlittle-endian] [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] [-mpic|-mno-pic]
Target TILE-Gx options: [-m32|-m64][-EB][-EL]
Target Visium options: [-mtune=arch]
Target Xtensa options: [--[no-]text-section-literals] [--[no-]auto-litpools] [--[no-]absolute-literals] [--[no-]target-align] [--[no-]longcalls] [--[no-]transform] [--rename-section oldname=newname] [--[no-]trampolines]
Target Z80 options: [-z80] [-r800] [ -ignore-undocumented-instructions] [-Wnud] [ -ignore-unportable-instructions] [-Wnup] [ -warn-undocumented-instructions] [-Wud] [ -warn-unportable-instructions] [-Wup] [ -forbid-undocumented-instructions] [-Fud] [ -forbid-unportable-instructions] [-Fup]
GNU as is really a family of assemblers. If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax.
as is primarily intended to assemble the output of the GNU C compiler "gcc" for use by the linker "ld". Nevertheless, we've tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly. This doesn't mean as always uses the same syntax as another assembler for the same architecture; for example, we know of several incompatible versions of 680x0 assembly language syntax.
Each time you run as it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.)
You give as a command line that has zero or more input file names. The input files are read (from left file name to right). A command line argument (in any position) that has no special meaning is taken to be an input file name.
If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type ctl-D to tell as there is no more program to assemble.
Use -- if you need to explicitly name the standard input file in your command line.
If the source is empty, as produces a small, empty object file.
as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly.
If you are invoking as via the GNU C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the -Wa) by commas. For example:
gcc -c -g -O -Wa,-alh,-L file.c
This passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table).
Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.)
Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively.
You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls.
The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64).
In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor.
If some implementations of a particular processor can have an extension, then then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions.
If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all.
The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default,
The following options are available when as is configured for an Alpha processor.
The following processor names are recognized: 21064, "21064a", 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a", "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6", "ev67", "ev68". The special name "all" may be used to allow the assembler to accept instructions valid for any Alpha processor.
In order to support existing practice in OSF/1 with respect to ".arch", and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the ``electro-vlasic'' names (e.g. "ev4") do not.
The following options are available when as is configured for an ARC processor.
The following options are available when as is configured for the ARM processor family.
The following options are available when as is configured for the Blackfin processor family.
See the info pages for documentation of the CRIS-specific options.
The following options are available when as is configured for a D10V processor.
The following options are available when as is configured for a D30V processor.
The following options are available when as is configured for an Epiphany processor.
The following options are available when as is configured for an H8/300 processor. @chapter H8/300 Dependent Features
The following options are available when as is configured for an i386 processor.
These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).
In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The following extensions are currently supported: 8087, 287, 387, 687, "no87", "no287", "no387", "no687", "mmx", "nommx", "sse", "sse2", "sse3", "ssse3", "sse4.1", "sse4.2", "sse4", "nosse", "nosse2", "nosse3", "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx", "avx2", "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap", "mpx", "sha", "rdpid", "ptwrite", "prefetchwt1", "clflushopt", "se1", "clwb", "avx512f", "avx512cd", "avx512er", "avx512pf", "avx512vl", "avx512bw", "avx512dq", "avx512ifma", "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq", "noavx512f", "noavx512cd", "noavx512er", "noavx512pf", "noavx512vl", "noavx512bw", "noavx512dq", "noavx512ifma", "noavx512vbmi", "noavx512_4fmaps", "noavx512_4vnniw", "noavx512_vpopcntdq", "vmx", "vmfunc", "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes", "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe", "ept", "lzcnt", "hle", "rtm", "invpcid", "clflush", "mwaitx", "clzero", "lwp", "fma4", "xop", "cx16", "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "svme", "abm" and "padlock". Note that rather than extending a basic instruction set, the extension mnemonics starting with "no" revoke the respective functionality.
When the ".arch" directive is used with -march, the ".arch" directive will take precedent.
Valid CPU values are identical to the processor list of -march=CPU.
The following options are available when as is configured for the Intel 80960 processor.
The following options are available when as is configured for the Ubicom IP2K series.
The following options are available when as is configured for the Renesas M32C and M16C processors.
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series.
The following options are available when as is configured for the Motorola 68000 series.
The following options are available when as is configured for an Altera Nios II processor.
The following options are available when as is configured for a Meta processor.
See the info pages for documentation of the MMIX-specific options.
The following options are available when as is configured for a NDS32 processor.
The following options are available when as is configured for a PowerPC processor.
The following options are available when as is configured for a RISC-V processor.
See the info pages for documentation of the RX-specific options.
The following options are available when as is configured for the s390 processor family.
The following options are available when as is configured for a TMS320C6000 processor.
The following values of arch are accepted: "c62x", "c64x", "c64x+", "c67x", "c67x+", "c674x".
The following options are available when as is configured for a TILE-Gx processor.
The following option is available when as is configured for a Visium processor.
The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
The following options are available when as is configured for an Xtensa processor.
The following options are available when as is configured for a Z80 family processor.
gcc(1), ld(1), and the Info entries for binutils and ld.
Copyright (c) 1991-2017 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled ``GNU Free Documentation License''.